Dynamic Scan: Driving Down the Cost of Test

D ire predictions about the soaring cost of semiconductor test are all too familiar. Two factors primarily drive this cost: the number of test patterns applied to each chip and the time it takes to run each pattern. For example, typical semiconductor testing for each chip involves a set of 1,000 to 5,000 test patterns—sets of input values and their associated (expected) output values. These test patterns are applied through scan chains that operate at about 25-100 MHz. Depending on the size of the scan chains on the chip, a set of test patterns can take a few seconds to execute per chip. It’s easy to see that even a small decrease in either the number of patterns or the time to execute them can quickly add up to big savings across millions of fabricated chips. This potential savings forms the basis for dynamic scan, a new approach to the wellestablished scan test methodology. Our initial studies, presented here, indicate that dynamic scan could easily reduce the time spent applying the test patterns by about 40 percent. A more theoretical analysis shows a potential savings of as much as 80 percent.